Volume No. :   10

Issue No. :  2

Year :  2018

ISSN Print :  0975-4393

ISSN Online :  2349-2988


Registration

Allready Registrered
Click to Login

An Efficient Design of 8-bit High Speed Parallel Prefix Adder



Address:   Garima Thakur, Harsh Sohal, Shruti Jain
Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan
*Corresponding Author
DOI No: 10.5958/2349-2988.2018.00015.3

ABSTRACT:
This paper discusses the comparison of various addition algorithms for different performance parameters like speed, area and power. We have studied and implemented different adders like ripple carry adder, carry skip adder, carry select adder, carry look ahead adder, Kogge stone adder and carry increment adder. To get great performance in processing system or in other multi-core devices, adders are always termed to be the most basic requirements. If the speed of adder improves or fastens, then there will be an automatic improvement in the speed of the system. Verilog coding is used for comparative analysis of various adders. Using Xilinx ISE 14.1 Design Suite various adders are simulated and synthesized for Spartan 3E FPGA. 4-bit Kogge stone adder was found to have less delay (8.608ns) and low power (0.042 W) than other 4-bit adders. The proposed 8-bit Carry increment adder using Kogge stone adder was implemented which has basic significant reduction in delay with 12.345ns and power with 0.054 W.
KEYWORDS:
Ripple Carry adder, Carry Skip adder, Carry Select adder, Carry look ahead adder, Kogge Stone adder, Carry Increment adder, Xilinx ISE 14.1.
Cite:
Garima Thakur, Harsh Sohal, Shruti Jain. An Efficient Design of 8-bit High Speed Parallel Prefix Adder. Research J. Science and Tech. 2018; 10(2):105-114.
[View HTML]     



Visitor's No. :   105289